1. Field of the Invention
The present invention relates to integrated circuit design and fabrication. More specifically, the present invention relates to a method and an apparatus to reduce random yield loss.
2. Related Art
As semiconductor manufacturing technologies move into deep sub-micron era, manufacturability and yield related issues are becoming increasingly important. In current processes, yield loss can be caused by many factors, which include random contamination particles, distortions of the printed features during the lithography process, thickness variations from the polishing process, etc. The portion of the yield loss that is caused by random contamination particles is referred to as random yield loss. Reducing the random yield loss is desirable because it can decrease manufacturing costs, thereby increasing the profitability of a semiconductor chip.